In the field of data storage microelectronic storage devices such as memories are being designed to store increasing amounts of data in ever smaller devices. This has led to faults within the devices becoming more common. Memories such as SRAM memories are therefore now being designed with some redundancy. This redundancy may be in the form of additional redundant rows and/or columns in each array. During testing of the array, errors can be detected and the redundant rows and/or columns can be used to replace the rows and/or columns having the errors within them. This means that the memories are repairable and provides a way of dealing with the increasing number of errors in such devices.
As each storage element within such an array is located within both a column and a row, the repair of a faulty element can be done using either a redundant row or column. Depending on the arrangement of other faulty locations in the memory it may be more efficient to repair an error with either a redundant row or a column. In order to correct the most number of errors present using the redundant rows and columns that are available various schemes for analysing the array have been devised. In one scheme a map of the whole array is made and a covering algorithm is then generated to arrange the redundant rows and columns to cover the maximum number of errors possible. This provides the best solution but is expensive in area to perform.
A simpler scheme for determining the best way of using the available redundant row and columns to cover the highest number of errors is described in “A Built-In Self-Repair Analyzer (CRESTA) for Embedded DRAMs” by Kawagoe et al, ITC International Test Conference 2000 pages 567-574. In this paper an array having two redundant rows and two redundant columns is considered, and the best repair solution is found deterministically by trying the spare rows and columns in different orders in real time RRCC, RCRC, RCCR, CRRC, CRCR, CCRR and finding the solution which covers most or all of the errors. This solution is then used to repair the memory.
A drawback of the “CRESTA” scheme is that the area required to provide the logic to implement the scheme is still considerable. Furthermore, with two redundant rows and columns the number of potential solutions is only six, however with an increasing number of redundant rows and columns this will increase dramatically. An increase in the potential number of solutions will make the “CRESTA” scheme more and more expensive in area.